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ee General Description Sh synchronous buck PWM The RT9214 is aa efficiency t high logic-supply voltages in PC based controllers that generate a systems..D high performance , single output devices These include internal soft-start, frequency compensation w w networks and integrates all of the control, output w adjustment, monitoring and protection functions into a
single package. The device operating at fixed 300kHz frequency provides an optimum compromise between efficiency, external component size, and cost. Adjustable over-current protection (OCP) monitors the voltage drop across the RDS(ON) of the lower MOSFET for synchronous buck PWM DC-DC controller. The overcurrent function cycles the soft-start in 4-times hiccup mode to provide fault protection, and in an always hiccup mode for under-voltage protection.
5V/12V Synchronous Buck PWM DC-DC Controller t4
Features
Operating with 5V or 12V Supply Voltage Drives All Low Cost N-Channel MOSFETs Voltage Mode PWM Control 300kHz Fixed Frequency Oscillator Fast Transient Response: - High-Speed GM Amplifier - Full 0 to 100% Duty Ratio Internal Soft-Start Adaptive Non-Overlapping Gate Driver Over-Current Fault Monitor on MOSFET, No Current Sense Resistor Required
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RT9214
Applications
Ordering Information
RT9214
Package Type S : SOP-8 Operating Temperature Range C : Commercial Standard P : Pb Free with Commercial Standard
Typical Application Circuit
+5V to +12V
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R1 10
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1 5 BOOT VCC FB GND 6 3
S a
2 8 7 4
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Graphic Card Motherboard, Desktop Servers IA Equipments Telecomm Equipments High Power DC-DC Regulators
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BOOT UGATE GND LGATE 2 3 4
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Pin Configurations
(TOP VIEW)
8 7 6 5 PHASE OPS FB VCC
SOP-8
D1 1N4148 C2 0.1uF Q1 MU ROCSET Q2 ML Q3 2N7002 L1 3uH C3 1uF
VIN +3.3V/+5V/+12V
C4 470uF
UGATE PHASE
C1 1uF
VOUT
RT9214
OPS
LGATE
C6 to C8 1000uFx3
Disable > R2 32 R3 68
R4 200-1k
C5 0.1-0.33uF
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Functional Pin Description
BOOT (Pin 1) Bootstrap supply pin for the upper gate driver. Connect the bootstrap capacitor between BOOT pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. UGATE (Pin 2) Upper gate driver output. Connect to the gate of highside power N-Channel MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. GND (Pin 3) Both signal and power ground for the IC. All voltage levels are measured with respect to this pin. Ties the pin directly to the low-side MOSFET source and ground plane with the lowest impedance. LGATE (Pin 4) Lower gate drive output. Connect to the gate of low-side power N-Channel MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. VCC (Pin 5) Connect this pin to a well-decoupled 5V or 12V bias supply. It is also the positive supply for the lower gate driver, LGATE. FB (Pin 6) Switcher feedback voltage. This pin is the inverting input of the error amplifier. FB senses the switcher output through an external resistor divider network. OPS (OCSET, POR and Shut-Down) (Pin 7) This pin provides multi-function of the over-current setting, UGATE turn-on POR sensing, and shut-down features. Connecting a resistor (ROCSET) between OPS and PHASE pins sets the over-current trip point. Pulling the pin to ground resets the device and all external MOSFETs are turned off allowing the output voltage power rails to float. This pin is also used to detect VIN in power on stage and issues an internal POR signal. PHASE (Pin 8) Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET.
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Function Block Diagram
VCC
EN
(3V_Logic & 3VDD_Analog)
0.8VREF
Oscillator (300kHz)
GND
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-
-
FB
+
+
-
+
0.6V
UV_S
Soft-Start & Fault Logic
OC
+
GM
EO
Gate Control Logic
-
Bias & Regulators
Reference
Power On Reset
+
PH_M
+ 0.1V 1.5V
3V
40uA
OPS
0.4V
+ BOOT UGATE PHASE
VCC
LGATE
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Absolute Maximum Ratings
(Note 1) Supply Voltage (VCC) ------------------------------------------------------------------------------------- 16V BOOT, VBOOT - VPHASE ------------------------------------------------------------------------------------ 16V PHASE to GND DC ------------------------------------------------------------------------------------------------------------- -5V to 15V < 200ns ------------------------------------------------------------------------------------------------------ -10V to 30V BOOT to PHASE ------------------------------------------------------------------------------------------ 15V BOOT to GND DC ------------------------------------------------------------------------------------------------------------- -0.3V to VCC+15V < 200ns ------------------------------------------------------------------------------------------------------ -0.3V to 42V UGATE ------------------------------------------------------------------------------------------------------- VPHASE - 0.3V to VBOOT + 0.3V LGATE ------------------------------------------------------------------------------------------------------- GND - 0.3V to VVCC + 0.3V Input, Output or I/O Voltage ----------------------------------------------------------------------------- GND-0.3V to 7V Power Dissipation, PD @ TA = 25C (Note 4) SOP-8 -------------------------------------------------------------------------------------------------------- 0.625W Package Thermal Resistance SOP-8, JA -------------------------------------------------------------------------------------------------- 160C/W Junction Temperature ------------------------------------------------------------------------------------- 150C Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------- 260C Storage Temperature Range ---------------------------------------------------------------------------- - 65C to 150C ESD Susceptibility (Note 2) HBM (Human Body Mode) ------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 3)
Supply Voltage, VCC -------------------------------------------------------------------------------------- 5V 5%,12V 10% Ambient Temperature Range ---------------------------------------------------------------------------- 0C to 70C Junction Temperature Range ---------------------------------------------------------------------------- 0C to 125C
Electrical Characteristics
(VCC = 5V/12V, TA = 25C, unless otherwise specified)
Parameter VCC Supply Current Nominal Supply Current Power-On Reset POR Threshold Hysteresis Switcher Reference Reference Voltage Oscillator Free Running Frequency Ramp Amplitude
Symbol
Test Conditions
Min
Typ
Max
Units
ICC
UGATE and LGATE Open
--
6
15
mA
VCCRTH VCCHYS VREF fOSC VOSC
VCC Rising
3.7 0.35 0.784
4.1 0.5 0.8
4.5 0.8 0.816
V V V
VCC = 12V VCC = 12V VCC = 12V
250 --
300 1.5
350 --
kHz VP-P
To be continued
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RT9214
Parameter Error Amplifier (GM) E/A Transconductance Open Loop DC Gain gm AO VBOOT - VPHASE = 12V, VUGATE - VPHASE = 6V VBOOT - VPHASE = 12V, VUGATE - VPHASE = 1V VCC = 12V, VLGATE = 6V VCC = 12V, VLGATE = 1V --0.7 90 --ms dB Symbol Test Conditions Min Typ Max Units
PWM Controller Gate Drivers (VCC = 12V) Upper Gate Source Upper Gate Sink Lower Gate Source Lower Gate Sink Dead Time Protection FB Under-Voltage Trip OC Current Source Soft-Start Interval FBUVT IOC TSS FB Falling VPHASE = 0V 70 35 -75 40 3.5 80 45 -% A ms IUGATE RUGATE ILGATE RLGATE TDT 300 -300 --500 4 500 3 --8 -5 100 mA mA ns
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. JA is measured in the natural convection at T A = 25C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard.
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Typical Operating Characteristics
(VOUT = 2.5V, unless otherwise specified ) Efficiency vs. Output Current
1 0.95 0.9
Efficiency vs. Output Current
1 0.95 0.9
Efficiency(%)
VCC = 12V VIN = 5V
0 5 10 15 20 25
Efficiency(%)
0.85 0.8 0.75 0.7 0.65 0.6
0.85 0.8 0.75 0.7 0.65 VCC = 5V VIN = 5V 0.6 0 5
10
15
20
25
Output Current (A)
Output Current (A)
Reference Voltage vs. Temperature
0.812 0.81
Frequency vs. Temperature
350
VCC = 12V VIN = 5V
Reference Voltage (V)
330
0.808 0.806 0.804 0.802 0.8 0.798 -40 -25 -10 5 20 35 50 65 80 95 110 125
Frequency (kHz)
310
290
270
250 -40 -10 20 50 80 110 140
Temperature (C)
Temperature (C)
POR vs. Temperature
4.75
VCC Switching
(100mV/Div)
POR Rising or Falling (V)
4.5
Rising
VOUT
4.25
IOUT UGATE
Falling
(10A/Div)
4
V CC
3.75
(20V/Div) VCC = 12Vto 5V IOUT= 10A VIN = 5V (10V/Div)
3.5 -40 -10 20 50 80 110 140
Time (10ms/Div)
Temperature (C)
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VCC Switching
(100mV/Div)
Power On
VOUT IOUT UGATE IOUT V CC
VCC = 5V to 12V IOUT= 10A, VIN = 5V (20V/Div) (10V/Div)
(500mV/Div)
VOUT
(10A/Div) (2A/Div)
UGATE
(10V/Div)
Time (10ms/Div)
Time (500us/Div)
Power Off
V CC VOUT
(10V/Div)
Dead Time (Rising)
VCC = VIN = 5V IOUT = 25A
UGATE VIN
(2V/Div)
(2V/Div)
PHASE (5V/Div) LGATE
UGATE
IOUT = 2A (10V/Div)
Time (5ms/Div)
Time (25ns/Div)
Dead Time (Falling)
VCC = 12V VIN = 5V IOUT= 25A
Transient Response (Rising)
UGATE
UGATE
(10V/Div)
VOUT PHASE (5V/Div)
(100mV/Div) VCC = VIN = 12V IOUT= 0A to 15A
LGATE
IL
(10A/Div) Freq. = 1/20ms, SR = 2.5A/us
L = 2.2uH C = 2000uF
Time (10ns/Div)
Time (5us/Div)
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Transient Response (Falling)
L = 2.2uH C = 2000uF
UGATE
(10V/Div)
VOUT
(100mV/Div) VCC = VIN = 12V IOUT= 15A to 0A Freq. = 1/20ms SR = 2.5A/us
IL
(10A/Div)
Time (25us/Div)
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Application Information
Inductor Selection The selection of output inductor is based on the considerations of efficiency, output power and operating frequency. Low inductance value has smaller size, but results in low efficiency, large ripple current and high output ripple voltage. Generally, an inductor that limits the ripple current (IL) between 20% and 50% of output current is appropriate. Figure 1 shows the typical topology of synchronous step-down converter and its related waveforms.
iS1 L + VL S1 VIN S2 iS2 + VOR +
According to Figure 1 the ripple current of inductor can be calculated as follows:
VIN - VOUT = L V IL D ; t = ; D = OUT t fs VIN VOUT VIN x fs x IL
L = (VIN - VOUT ) x
(1)
Where: VIN = Maximum input voltage VOUT = Output Voltage t = S1 turn on time
IL iC rC IOUT + RL VOUT -
IL = Inductor current ripple fS = Switching frequency D = Duty Cycle rC = Equivalent series resistor of output capacitor Output Capacitor
VOC -
+
COUT
TS Vg1 Vg2 VIN - VOUT VL - VOUT TON TOFF
The selection of output capacitor depends on the output ripple voltage requirement. Practically, the output ripple voltage is a function of both capacitance value and the equivalent series resistance (ESR) rC. Figure 2 shows the related waveforms of output capacitor.
iL diL VIN-VOUT = L dt diL VOUT dt = L IOUT TS
iL IL IL = IOUT
iC 0 1/2IL IL
iS1
VOC
VOC
iS2
VOR IL x rc 0
Figure 1. The waveforms of synchronous step-down converter
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t1
t2
Figure 2. The related waveforms of output capacitor
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RT9214
The AC impedance of output capacitor at operating frequency is quite smaller than the load impedance, so the ripple current (IL) of the inductor current flows mainly through output capacitor. The output ripple voltage is described as:
VOUT = VOR + VOC 1 t2 VOUT = IL x rc + ic dt CO t1 1 VOUT 2 VOUT = IL x IL x rc + (1- D)T S 8 COL
ZOUT is the shut impedance at the output node to ground (see Figure 3 and Figure 4),
GM C1 R1 VOUT C2
(2) (3) (4)
where VOR is caused by ESR and VOC by capacitance. For electrolytic capacitor application, typically 90 to 95% of the output voltage ripple is contributed by the ESR of output capacitor. So Equation (4) could be simplified as:
Figure 3. A Type 2 error-amplifier with shut network to ground
VOUT RO
+ EA+ EA+ GM
VOUT = IL x rc
(5)
Users could connect capacitors in parallel to get calculated ESR. Input Capacitor The selection of input capacitor is mainly based on its maximum ripple current capability. The buck converter draws pulsewise current from the input capacitor during the on time of S1 as shown in Figure 1. The RMS value of ripple current flowing through the input capacitor is described as:
Irms = IOUT D(1 - D) (A)
Figure 4. Equivalent circuit Pole and Zero :
FP =
1 1 ; FZ = 2 x R1C 2 2 x R1C1
We can see the open loop gain and the Figure 3 whole loop gain in Figure 5.
(6)
Open Loop, Unloaded Gain
Gain (dB)
The input capacitor must be cable of handling this ripple current. Sometime, for higher efficiency the low ESR capacitor is necessarily. PWM Loop Stability RT9214 is a voltage mode buck converter using the high gain error amplifier with transconductance (OTA, Operational Transconductance Amplifier). The transconductance :
dI GM = OUT dVm
A FZ
Closed Loop, Unloaded Gain
FP Gain = GMR1
B
100
1000
10k
100k
Frequency (Hz)
Figure 5. Gain with the Figure 2 circuit RT9214 internal compensation loop: GM = 0.7ms , R1=75k , C1 = 6.4nF , C2 = 10pF
The mid-frequency gain :
dVOUT = dIOUT Z OUT = GMdVIN Z OUT dVOUT G= = GMZ OUT dVIN
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OPS (Over Current Setting, VIN_POR and Shutdown) 1.OCP Sense the low-side MOSFET' s RDS(ON) to set over-current trip point. Connecting a resistor (ROCSET) from this pin to the source of the upper MOSFET and the drain of the lower MOSFET sets the over-current trip point. ROCSET, an internal 40A current source, and the lower MOSFET on resistance, RDS(ON), set the converter over-current trip point (IOCSET) according to the following equation:
I OCSET = 40uA x R OCSET - 0.4V
R DS(ON) of the lower MOSFET
OPS pin function is similar to RC charging or discharging circuit, so the over-current trip point is very sensitive to parasitic capacitance (ex. shut-down MOSFET) and the duty ratio. Below Figures say those effect. And test conditions are Rocset = 15k (over -current trip point = 20.6A), Low-side MOSFET is IR3707.
OCP
OCP
UGATE (10V/Div)
UGATE (10V/Div)
IL (10A/Div) OPS (200mV/Div) VIN = 5V, VCC = 12V VOUT = 1.5V VIN = 5V, VCC = 12V VOUT = 1.5V
IL (10A/Div)
Time (5s/Div)
Time (5s/Div)
OCP
OCP
OPS (200mV/Div)
UGATE (10V/Div) UGATE (10V/Div) IL (10A/Div) IL (10A/Div) VIN = 12V, VCC = 12V VOUT = 1.5V VIN = 12V, VCC = 12V VOUT = 1.5V
Time (2.5s/Div)
Time (2.5s/Div)
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2. VIN_POR UGATE will continuously generate a 10kHz colck with 1% duty cycle before VIN is ready. VIN is recognized ready by detecting VOPS crossing 1.5V four times (rising & falling). ROCSET must be kept lower than 37.5k for large ROCSET will keep VOPS always higher than 1.5V. Figure 6 shows the detail actions of OCP and POR. It is highly recommend-ed that ROCSET be lower than 30k.
3V
1) Mode 1 (SS< Vramp_valley) Initially the COMP stays in the positive saturation. When SS< VRAMP_Valley, there is no non-inverting input available to produce duty width. So there is no PWM signal and VOUT is zero. 2) Mode 2 (VRAMP_Valley< SS< Cross-over) When SS>VRAMP_Valley, SS takes over the non-inverting input and produce the PWM signal and the increasing duty width according to its magnitude above the ramp signal. The output follows the ramp signal, SS. However while VOUT increases, the difference between VOUT and SSE (SS - VGS) is reduced and COMP leaves the saturation and declines. The takeover of SS lasts until it meets the COMP. During this interval, since the feedback path is broken, the converter is operated in the open loop. 3) Mode3 ( Cross-over< SS < VGS + VREF) When the Comp takes over the non-inverting input for PWM Amplifier and when SSE (SS - VGS) < VREF, the output of the converter follows the ramp input, SSE (SS - VGS). Before the crossover, the output follows SS signal. And when Comp takes over SS, the output is expected to follow SSE (SS - VGS). Therefore the deviation of VGS is represented as the falling of VOUT for a short while. The COMP is observed to keep its decline when it passes the cross-over, which shortens the duty width and hence the falling of VOUT happens. Since there is a feedback loop for the error amplifier, the output' s response to the ramp input, SSE (SS - VGS) is lower than that in Mode 2. 4) Mode 4 (SS > VGS + VREF) When SS > VGS + VREF, the output of the converter follows the desired VREF signal and the soft start is completed now.
40uA ROCSET OC
+
0.4V 10pF
OPS Cparasitic
PHASE
Q2 DISABLE
+ -
VIN POR_H PHASE_M
+ -
UGATE 1.5V
1st 2nd 3rd 4th OPS waveform (1) Internal Counter will count (VOPS > 1.5V) four times (rising & falling) to recognize VIN is ready. (2) ROCSET can set too large. Or can be detect VIN is ready (counter = 1, not equal 4)
Figure 6. OCP and VIN_POR actions 3. Shutdown Pulling low the OPS pin by a small single transistor can shutdown the RT9214 PWM controller as shown in typical application circuit. Soft Start A built-in soft-start is used to prevent surge current from power supply input during power on. The soft-start voltage is controlled by an internal digital counter. It clamps the ramping of reference voltage at the input of error amplifier and the pulse-width of the output driver slowly. The typical soft-start duration is 3ms.
COMP
VRAMP_Valley Cross-over
SS_Internal VCORE SSE_Internal
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Under Voltage Protection The voltage at FB pin is monitored and protected against UV (under voltage). The UV threshold is the FB or FBL under 80%. UV detection has 15s triggered delay. When OC is trigged, a hiccup restart sequence will be initialized, as shown in Figure 7 Only 4 times of trigger are allowed to latch off. Hiccup is disabled during soft-start interval, but UV_FB has some difference from OC, it will always trigger VIN power sensing after 4 times hiccup, as shown in Figure 8.
COUNT = 1
Internal
placement layout and printed circuit design can minimize the voltage spikes induced in the converter. Consider, as an example, the turn-off transition of the upper MOSFET prior to turn-off, the upper MOSFET was carrying the full load current. During turn-off, current stops flowing in the upper MOSFET and is picked up by the low side MOSFET or schottky diode. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selections, layout of the critical components, and use shorter and wider PCB traces help in minimizing the magnitude of voltage spikes. There are two sets of critical components in a DC-DC converter using the RT9214. The switching power components are most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. The power components and the PWM controller should be placed firstly. Place the input capacitors, especially the high-frequency ceramic decoupling capacitors, close to the power switches. Place the output inductor and output capacitors between the MOSFETs and the load. Also locate the PWM controller near by MOSFETs. A multi-layer printed circuit board is recommended.
COUNT = 2
COUNT = 3
COUNT = 4
4V
SS
2V 0V OVERLOAD APPLIED
Inductor Current
0A T0 T1 T2 TIME T3 T4
Figure 7. UV and OC trigger hiccup mode
Power Off
UGATE FB VOUT VIN
(20V/Div) (500mV/Div)
UV
VIN Power Sensing
(2V/Div) (2V/Div) IOUT = 2A
Time (10ms/Div)
Figure 8, UV_FB trigger VIN power sensing PWM Layout Considerations MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency and radiate noise, that results in over-voltage stress on devices. Careful component
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Figure 9 shows the connections of the critical components in the converter. Note that the capacitors CIN and COUT each of them represents numerous physical capacitors. Use a dedicated grounding plane and use vias to ground all critical components to this layer. Apply another solid layer as a power plane and cut this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the PHASE node, but it is not necessary to oversize this particular island. Since the PHASE node is subjected to very high dV/dt voltages, the stray capacitance formed between these island and the surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal routing. The PCB traces between the PWM controller and the gate of MOSFET and also the traces connecting source of MOSFETs should be sized to carry 2A peak currents.
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RT9214
IQ1 5V/12V Q1 IQ2 Q2 GND
+ +
IL VOUT
+
LOAD
GND LGATE VCC RT9214 UGATE FB
Figure 9. The connections of the critical components in the converter Below PCB gerber files are our test board for your reference:
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According to our test experience, you must still notice two items to avoid noise coupling: 1.The ground plane should not be separated. 2.VCC rail adding the LC filter is recommended.
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RT9214
Outline Dimension
A
H M
J
B
F
C I D
Dimensions In Millimeters Symbol Min A B C D F H I J M 4.801 3.810 1.346 0.330 1.194 0.178 0.102 5.791 0.406 Max 5.004 3.988 1.753 0.508 1.346 0.254 0.254 6.198 1.270
Dimensions In Inches Min 0.189 0.150 0.053 0.013 0.047 0.007 0.004 0.228 0.016 Max 0.197 0.157 0.069 0.020 0.053 0.010 0.010 0.244 0.050
8-Lead SOP Plastic Package
RICHTEK TECHNOLOGY CORP.
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
RICHTEK TECHNOLOGY CORP.
Taipei Office (Marketing) 8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
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